The invention relates to clock signals. More particularly, the invention relates to methods and equipment for producing one or more clock signals from delayed versions of a given clock signal.
FIG. 1 is a simplified block diagram of a processor 105 and its environment 100. The processor 105 comprises a core 110 and an I/O interface 115. The I/O interface 115 connects the processor 105 to a bus 120. One or more other devices, such as the devices 125 and 130, are also connected to the bus 120. The other devices 125 and 130 may be storage devices, such as RAM memory or disk drives, peripherals, such as printers or data communication devices, or other processors, for example.
The processor core 110 is paced by a core clock. Rather than operating in a continuous manner, the processor core 110, like all digital electronic devices, operates discretely. The processor core 110 performs operations upon every cycle of the processor clock. The core clock is the xe2x80x9cheartbeatxe2x80x9d of the of the processor core 110. As used herein, the term xe2x80x9cclock,xe2x80x9d refers to any signal having a periodic property. Clock signals used with digital electronics are typically periodic rectangular waveforms oscillating between two (binary) states (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d), and the significant periodic property is typically a rising edge (i.e., the transition from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d) when edge sensitive clocking is utilized. The processor core 110 advances in operation every time there is a rising and/or falling edge on the core clock.
The bus 120 is paced by a bus clock, whose rate or frequency (the two words are synonymous in this context) is physically constrained to be slower than the core clock. Rather than letting the bus clock and the core clock run asynchronously, the frequency of the core clock is typically an integer multiple of the bus clock, and the bus and core clock are phase-locked in some way, such as, for example, every rising edge of the bus clock occurring approximately simultaneously with a rising edge of core clock. For example, the frequency of the core clock might be 1 GHz (109 cycles per second) and the frequency of the bus clock might be 250 MHz (250xc3x97106 cycles per second), in which case the core-bus clock frequency ratio is four (or four-to-one, xe2x80x9c4:1xe2x80x9d). A faster core clock enables the processor 105 to operate more efficiently by performing several operations for each access to the bus 120. The slower bus clock can be generated from the faster core clock by frequency division. Frequency division, though very simple, is available only for cases in which the frequency ratio is an whole number. Alternatively, the faster core clock can be generated from the slower bus clock using a phase locked loop (PLL). Though a PLL can be designed to operate at almost any frequency ratio, a PLL works best for a single, fixed frequency ratio.
Challenges are encountered when the core-bus clock frequency ratio is not fixed. This situation may arise, for example, when the processor 105 is meant to be fielded in different environments 100, each environment 100 having a bus 120 that has a different maximum bus speed for some reason. For example, in one environment 100, the processor 105 may be the only processor on the bus 120, the core frequency might be 1 GHz and the bus frequency 250 MHz, in which case the core-bus clock frequency ratio would be four. In another environment 100, the device 125 may be another processor and the bus frequency would need to slow from 250 MHz to 125 MHz in order to handle both processors, resulting in a core-bus clock frequency ratio that is eight (or 16:2). In actual practice, the relationship between the number of processors on the bus 120 and the core-bus frequency ratio is often not as simple as the linear relationship just illustrated, but it is generally true that a greater number of processors on the bus 120 decreases the bus frequency and hence increases the core-bus clock frequency ratio. Thus, in a third environment 100 when the device 130 is a third processor, then the core-bus frequency ratio would be even higher (perhaps 12:1, 17:2 or 28:3, for example). This situation may arise, for example, when the number of processors on the bus 120 dynamically changes.
For a PLL to be able to handle variable core-bus clock frequency ratios, the frequency range of the PLL must be very large. This is undesirable because it results in a poorer dynamic response. It is also disadvantageous for the loop to have to re-lock every time the ratio is changed. Re-locking requires time for the PLL to settle to a new locked state. A poor dynamic response further slows settling and exacerbates the problem.
In one respect, the invention is an apparatus for producing one or more clock signals. The apparatus comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal is fed through the plurality of delay elements, producing several delayed versions of the clock signal. The logic circuitry selects and combines the delayed versions of the clock signal to produce one or more output clock signals, each having a frequency that is a desired rational multiple less than one (i.e., a fraction) of the frequency of the clock signal fed through the plurality of delay elements.
In another respect, the invention is a method of producing an output clock signal. Starting with a given clock signal, the method delays the given clock signal N times sequentially, where N is a natural number. The method then selects a series of time splices of the delayed clock signals, so as to produce the output clock signal. Optionally, the method can lock the given clock signal to a reference clock signal. The frequency of the output clock signal can be set to be (N/M)xc3x97fREF, where M is a natural number (i.e., positive integer) and fREF is the frequency of the reference clock signal. The reference signal may be a processor core clock signal, and the output clock signal may be an external I/O clock signal.
In comparison to other solutions, certain embodiments of the invention are capable of achieving certain advantages, including the following: (1) certain embodiments can flexibly produce a large variety of output clock frequencies and frequency ratios; (2) in locking arrangements, the dynamic response is independent of the output frequency range and can be optimized to a single reference frequency; (3) certain embodiments need not re-lock to produce a different output frequency; (4) the circuitry of certain embodiments requires less area than a PLL; and (5) certain embodiments offer improved ability to decrease clock skew across a processor or other digital electronic device.
Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the drawings.